Share Email Print

Proceedings Paper

Standard cell electrical and physical variability analysis based on automatic physical measurement for design-for-manufacturing purposes
Author(s): Eitan Shauly; Allon Parag; Hafez Khmaisy; Uri Krispil; Ofer Adan; Shimon Levi; Sergey Latinski; Ishai Schwarzband; Israel Rotstein
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

A fully automated system for process variability analysis of high density standard cell was developed. The system consists of layout analysis with device mapping: device type, location, configuration and more. The mapping step was created by a simple DRC run-set. This database was then used as an input for choosing locations for SEM images and for specific layout parameter extraction, used by SPICE simulation. This method was used to analyze large arrays of standard cell blocks, manufactured using Tower TS013LV (Low Voltage for high-speed applications) Platforms. Variability of different physical parameters like and like Lgate, Line-width-roughness and more as well as of electrical parameters like drive current (Ion), off current (Ioff) were calculated and statistically analyzed, in order to understand the variability root cause. Comparison between transistors having the same W/L but with different layout configurations and different layout environments (around the transistor) was made in terms of performances as well as process variability. We successfully defined "robust" and "less-robust" transistors configurations, and updated guidelines for Design-for-Manufacturing (DfM).

Paper Details

Date Published: 4 April 2011
PDF: 7 pages
Proc. SPIE 7974, Design for Manufacturability through Design-Process Integration V, 797410 (4 April 2011); doi: 10.1117/12.881841
Show Author Affiliations
Eitan Shauly, Tower Semiconductor Ltd. (Israel)
Technion-Israel Institute of Technology (Israel)
Allon Parag, Tower Semiconductor Ltd. (Israel)
Hafez Khmaisy, Tower Semiconductor Ltd. (Israel)
Uri Krispil, Mentor Graphics Corp. (Israel)
Ofer Adan, Applied Materials, Inc. (Israel)
Shimon Levi, Applied Materials, Inc. (Israel)
Sergey Latinski, Applied Materials, Inc. (Israel)
Ishai Schwarzband, Applied Materials, Inc. (Israel)
Israel Rotstein, Tower Semiconductor Ltd. (Israel)

Published in SPIE Proceedings Vol. 7974:
Design for Manufacturability through Design-Process Integration V
Michael L. Rieger, Editor(s)

© SPIE. Terms of Use
Back to Top