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Proceedings Paper

Spacer-defined double patterning for 20nm and beyond logic BEOL technology
Author(s): Ryoung-Han Kim; Chiew-seng Koay; Sean D. Burns; Yunpeng Yin; John C. Arnold; Christopher Waskiewicz; Sanjay Mehta; Martin Burkhardt; Matthew E. Colburn; Harry J. Levinson
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Paper Abstract

Spacer-defined double patterning was investigated as a patterning option for 20/14-nm logic technology's back-end-of-line (BEOL), and compared with the double patterning options of front-end-of-line (FEOL). Negative spacer-defined double patterning was used to provide less overlay impact and variable CD control on the metal lines compared with other double patterning techniques. Block lithography as a 2nd exposure was able to maintain better tip-to-tip and tip-to-line fidelity by forming lines that behave as a additive etch block. SiO2 spacer was directly deposited on resist core-mandrel via a low-temperature deposition process. Resist integrity was optimized through aerial image and mask optimization as well as resist selection processes. Design decomposition of the BEOL layout was identified as a major challenge in enabling the spacer-defined double patterning. Finally, successful integration of the patterning into the BEOL device was demonstrated.

Paper Details

Date Published: 22 March 2011
PDF: 13 pages
Proc. SPIE 7973, Optical Microlithography XXIV, 79730N (22 March 2011); doi: 10.1117/12.881701
Show Author Affiliations
Ryoung-Han Kim, GLOBALFOUNDRIES Inc. (United States)
Chiew-seng Koay, IBM Research (United States)
Sean D. Burns, IBM Research (United States)
Yunpeng Yin, IBM Research (United States)
John C. Arnold, IBM Research (United States)
Christopher Waskiewicz, IBM Research (United States)
Sanjay Mehta, IBM Research (United States)
Martin Burkhardt, IBM Research (United States)
Matthew E. Colburn, IBM Research (United States)
Harry J. Levinson, GLOBALFOUNDRIES Inc. (United States)


Published in SPIE Proceedings Vol. 7973:
Optical Microlithography XXIV
Mircea V. Dusa, Editor(s)

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