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Proceedings Paper

Defect-aware reticle floorplanning for EUV masks
Author(s): Abde Ali Kagalwalla; Puneet Gupta; Duck-Hyung Hur; Chul-Hong Park
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Paper Abstract

Fabricating defect-free mask blanks remains a major "show-stopper" for adoption of EUV lithography. One promising approach to alleviate this problem is reticle floorplanning with the goal of minimizing the design impact of buried defects. In this work, we propose a simulated annealing based gridded floorplanner for single project reticles that minimizes the design impact of buried defects. Our results show a substantial improvement in mask yield with this approach. For a 40-defect mask, our approach can improve mask yield from 53% to 94%. If additional design information is available, it can be exploited for more accurate yield computation and further improvement in mask yield, up to 99% for a 40-defect mask. These improvements are achieved with a limited area overhead of 0.03% on the exposure field. Defect-aware floorplanning also reduces sensitivity of mask yield to defect dimensions.

Paper Details

Date Published: 5 April 2011
PDF: 10 pages
Proc. SPIE 7974, Design for Manufacturability through Design-Process Integration V, 79740Z (5 April 2011); doi: 10.1117/12.881667
Show Author Affiliations
Abde Ali Kagalwalla, Univ. of California, Los Angeles (United States)
Puneet Gupta, Univ. of California, Los Angeles (United States)
Duck-Hyung Hur, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Chul-Hong Park, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)


Published in SPIE Proceedings Vol. 7974:
Design for Manufacturability through Design-Process Integration V
Michael L. Rieger, Editor(s)

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