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Proceedings Paper

Spacer defined double patterning for (sub-)20nm half pitch single damascene structures
Author(s): Janko Versluijs; Yong Kong Siew; Eddy Kunnen; Diziana Vangoidsenhoven; Steven Demuynck; Vincent Wiaux; Harold Dekkers; Gerald Beyer
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Paper Abstract

The spacer defined double patterning (SDDP) approach for 20nm half pitch (HP) single damascene Cu interconnect structures using immersion lithography is being reviewed. Final results on wafer will be shown, focusing on critical double patterning topics such as CD & overlay budget and line edge roughness (LER); and their impact on the electrical functioning of the back-end-of-line test structures. The feasibility of extending the SDDP technique down to 15nm HP structures is also discussed. The 30nm line/space structures patterned in resist, required as a starting point for this exercise, will be patterned using EUV lithography.

Paper Details

Date Published: 22 March 2011
PDF: 11 pages
Proc. SPIE 7973, Optical Microlithography XXIV, 79731R (22 March 2011); doi: 10.1117/12.881600
Show Author Affiliations
Janko Versluijs, IMEC (Belgium)
Yong Kong Siew, IMEC (Belgium)
Eddy Kunnen, IMEC (Belgium)
Diziana Vangoidsenhoven, IMEC (Belgium)
Steven Demuynck, IMEC (Belgium)
Vincent Wiaux, IMEC (Belgium)
Harold Dekkers, IMEC (Belgium)
Gerald Beyer, IMEC (Belgium)

Published in SPIE Proceedings Vol. 7973:
Optical Microlithography XXIV
Mircea V. Dusa, Editor(s)

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