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Proceedings Paper

A state-of-the-art hotspot recognition system for full chip verification with lithographic simulation
Author(s): Mark C. Simmons; Jae-Hyun Kang; Youngkeun Kim; Joung Il Park; Seung weon Paek; Kee-sup Kim
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Paper Abstract

In today's semiconductor industry, prior to wafer fabrication, it has become a desirable practice to scan layout designs for lithography-induced defects using advanced process window simulations in conjunction with corresponding manufacturing checks. This methodology has been proven to provide the highest level of accuracy when correlating systematic defects found on the wafer with those identified through simulation. To date, when directly applying this methodology at the full chip level, there has been unfavorable expenses incurred that are associated with simulation which are currently overshadowing its primary benefit of accuracy - namely, long runtimes and the requirement for an abundance of cpus. Considering the aforementioned, the industry has begun to lean towards a more practical application for hotspot identification that revolves around topological pattern recognition in an attempt to sidestep the simulation runtime. This solution can be much less costly when weighing against the negative runtime overhead of simulation. The apparent benefits of pattern matching are, however, counterbalanced with a fundamental concern regarding detection accuracy; topological pattern identification can only detect polygonal configurations, or some derivative of a configuration, which have been previously identified. It is evident that both systems have their strengths and their weaknesses, and that one system's strength is the other's weakness, and vice-versa. A novel hotspot detection methodology that utilizes pattern matching combined with lithographic simulation will be introduced. This system will attempt to minimize the negative aspects of both pattern matching and simulation. The proposed methodology has a high potential to decrease the amount of processing time spent during simulation, to relax the high cpu count requirement, and to maximize pattern matching accuracy by incorporating a multi-staged pattern matching flow prior to performing simulation on a reduced data set. Also brought forth will be an original methodology for constructing the core pattern set, or candidate hotspot library, in conjunction with establishing hotspot and coldspot pattern libraries. Lastly, it will be conveyed how this system can automatically improve its potential as more designs are passed through it.

Paper Details

Date Published: 4 April 2011
PDF: 9 pages
Proc. SPIE 7974, Design for Manufacturability through Design-Process Integration V, 79740M (4 April 2011); doi: 10.1117/12.881596
Show Author Affiliations
Mark C. Simmons, Mentor Graphics Corp. (United States)
Jae-Hyun Kang, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Youngkeun Kim, Mentor Korea Co., Ltd. (Korea, Republic of)
Joung Il Park, Mentor Korea Co., Ltd. (Korea, Republic of)
Seung weon Paek, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Kee-sup Kim, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)

Published in SPIE Proceedings Vol. 7974:
Design for Manufacturability through Design-Process Integration V
Michael L. Rieger, Editor(s)

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