Share Email Print
cover

Proceedings Paper

Sidewall spacer quadruple patterning for 15nm half-pitch
Author(s): Ping Xu; Yongmei Chen; Yijian Chen; Liyan Miao; Shiyu Sun; Sung-Woo Kim; Ami Berger; Daxin Mao; Christ Bencher; Raymond Hung; Chris Ngai
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

193nm immersion lithography, with the single-exposure resolution limitation of half-pitch 38nm, has extended its patterning capability to about 20nm using the double-patterning technique[1]. Despite the non-trivial sub-20nm patterning challenges, several NAND Flash manufacturers are already pursuing for sub-16nm patterning technology. 25nm NAND flash memory has already begun production in 2010, and given the typical 2-year scaling cycle, sub-16nm NAND devices should see pilot or mass production as early as 2014. Using novel patterning techniques such as sidewall spacer quadruple patterning (upon 120nm to 128nm pitch using dry ArF lithography) or triple patterning (upon 90nm pitch using immersion ArF lithography), we are able to extend optical lithography to sub-16nm half-pitch and demonstrate the lithographic performance that can nearly meet the ITRS roadmap requirements. In this paper, we conduct an in-depth review and demonstration of sidewall spacer quadruple patterning; including 300mm wafer level data of the mean values and CDU along with a mathematical assessment of the various data pools for sub-16nm lines and spaces. By understanding which processes (lithography, deposition, and etch) define the critical dimension of each data pool, we can make predictions of CDU capability for the sidewall spacer quad patterning. Our VeritySEM4i CD SEM tool demonstrated high measurement yield during fully automated measurements, which enables accurate lines, spaces and CDU measurements of the sub-16nm. The patterns generated from the sidewall spacer quadruple patterning techniques are used as a hardmask to transfer sub-16nm lines and spaces patterns to underneath amorphous silicon and silicon oxide layers, or poly silicon layer for 1X STI or poly gate applications.

Paper Details

Date Published: 23 March 2011
PDF: 12 pages
Proc. SPIE 7973, Optical Microlithography XXIV, 79731Q (23 March 2011); doi: 10.1117/12.881547
Show Author Affiliations
Ping Xu, Applied Materials, Inc. (United States)
Yongmei Chen, Applied Materials, Inc. (United States)
Yijian Chen, Applied Materials, Inc. (United States)
Liyan Miao, Applied Materials, Inc. (United States)
Shiyu Sun, Applied Materials, Inc. (United States)
Sung-Woo Kim, Applied Materials, Inc. (United States)
Ami Berger, Applied Materials, Inc. (Israel)
Daxin Mao, Applied Materials, Inc. (United States)
Christ Bencher, Applied Materials, Inc. (United States)
Raymond Hung, Applied Materials, Inc. (United States)
Chris Ngai, Applied Materials, Inc. (United States)


Published in SPIE Proceedings Vol. 7973:
Optical Microlithography XXIV
Mircea V. Dusa, Editor(s)

© SPIE. Terms of Use
Back to Top