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Proceedings Paper

The effective etch process proximity correction methodology for improving on chip CD variation in 20 nm node DRAM gate
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Paper Abstract

This paper presents an effective methodology for etch PPC (Process Proximity Correction) of 20 nm node DRAM (Dynamic Random Access Memory) gate transistor. As devices shrinks, OCV(On chip CD Variation) control become more important to meet the performance goal for high speed in DRAM. The main factors which influence OCV are mask, photo, etch PPE (Process proximity effect) in DRAM gate. Model based etch PPC is required to properly correct Etch PPE as device density increases. To improve OCV in DRAM gate, we applied new type of etch loading kernel. It is called Vkernel which accounts for directional weight from the point of interest. And we optimized the etch PPC convergence by optimizing the etch PPC iteration. Because of density difference between spider mask and real gate mask, the skew difference occurs between them. We tested the effect of long range density using same real gate pattern clip by varying mask open image size from 0.5 ~ 10 mm. The ADI CD difference was on average in the order on 2 nm for varying mask open image size. But the ACI CD difference (the average of CD range by varying open image size) was very noticeable (about 15 nm). This result shows that etch skew affected by long range density by mm unit size. Due to asymmetrical pattern in real gate mask, spider mask which have symmetrical patterns is necessarily used to make PPC model. The etch skew of real pattern clip in spider mask was not also the same for the real pattern in real gate mask. To reduce this skew difference between spider mask and real mask, we applied open field mask correction term and long range density effects correlation equation to PPC modeling. There was noticeable improvement in the accuracy of PPC model. By applying these improvement items, OCV of 20 nm node DRAM gate is shown to improve up to 67%.

Paper Details

Date Published: 5 April 2011
PDF: 10 pages
Proc. SPIE 7974, Design for Manufacturability through Design-Process Integration V, 79740Y (5 April 2011); doi: 10.1117/12.881472
Show Author Affiliations
Jeong-Geun Park, Hanyang Univ. (Korea, Republic of)
Sang-wook Kim, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Seong-Bo Shim, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Sung-Soo Suh, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Hye-Keun Oh, Hanyang Univ. (Korea, Republic of)


Published in SPIE Proceedings Vol. 7974:
Design for Manufacturability through Design-Process Integration V
Michael L. Rieger, Editor(s)

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