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Proceedings Paper

In-design DFM CMP flow for block level simulation using 32nm CMP model
Author(s): Naya Ha; Jinwoo Lee; S. W. Paek; Kee Sup Kim; Kuang Han Chen; Aaron Gower-Hall; Tamba Gbondo-Tugbawa; Philippe Hurat
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Paper Abstract

Traditionally model based CMP check and hotspot detection are only done at the top level of the design because full chip assembly is required to capture CMP long range effect. When manufacturing hotspots are found just before tape out and layout modification is required, this can disrupt the overall schedule by repeating the verification steps with the changed layout. Hence getting feedback at early design stage is critical to ensure that the design is correct by construction. In this paper, we present a model-based CMP-DFM methodology which is used at early design phases to avoid CMP related manufacturing failures. An accurate CMP model has been developed and used to predict surface topographies for 32nm designs as well as physical hotspots caused by dishing, erosion, and depth of focus. We demonstrate how to apply a characterized 32nm CMP physical model to run block level simulation with little or no context information. The block level simulation methodology allows designers to check block robustness against any possible surrounding environments in which the block may be placed. This approach can be taken for corner case analysis in CMP-aware RC extraction.

Paper Details

Date Published: 4 April 2011
PDF: 7 pages
Proc. SPIE 7974, Design for Manufacturability through Design-Process Integration V, 79740W (4 April 2011); doi: 10.1117/12.880899
Show Author Affiliations
Naya Ha, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Jinwoo Lee, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
S. W. Paek, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Kee Sup Kim, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Kuang Han Chen, Cadence Design Systems, Inc. (United States)
Aaron Gower-Hall, Cadence Design Systems, Inc. (United States)
Tamba Gbondo-Tugbawa, Cadence Design Systems, Inc. (United States)
Philippe Hurat, Cadence Design Systems, Inc. (United States)


Published in SPIE Proceedings Vol. 7974:
Design for Manufacturability through Design-Process Integration V
Michael L. Rieger, Editor(s)

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