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Proceedings Paper

Double patterning compliant logic design
Author(s): Yuangsheng Ma; Jason Sweis; Chris Bencher; Yunfei Deng; Huixiong Dai; Hidekazu Yoshida; Bimal Gisuthan; Jongwook Kye; Harry J. Levinson
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Paper Abstract

Double patterning technology (DPT) is the only solution to enable the scaling for advanced technology nodes before EUV or any other advanced patterning techniques become available. In general, there are two major double patterning techniques: one is Litho-Etch-Litho-Etch (LELE), and the other is sidewall spacer technology, a Self-Aligned Double Patterning technique (SADP). While numerous papers have previously demonstrated these techniques on wafer process capabilities and processing costs, more study needs to be done in the context of standard cell design flow to enable their applications in mass production. In this paper, we will present the impact of DPT on logic designs, and give a thorough discussion on how to make DPT-compliant constructs, placement and routing using examples with Cadence's Encounter Digital Implementation System (EDI System).

Paper Details

Date Published: 4 April 2011
PDF: 12 pages
Proc. SPIE 7974, Design for Manufacturability through Design-Process Integration V, 79740D (4 April 2011); doi: 10.1117/12.879846
Show Author Affiliations
Yuangsheng Ma, GLOBALFOUNDRIES Inc. (United States)
Jason Sweis, Cadence Design Systems, Inc. (United States)
Chris Bencher, Applied Materials, Inc. (United States)
Yunfei Deng, GLOBALFOUNDRIES Inc. (United States)
Huixiong Dai, Applied Materials, Inc. (United States)
Hidekazu Yoshida, GLOBALFOUNDRIES Inc. (United States)
Bimal Gisuthan, Cadence Design Systems, Inc. (United States)
Jongwook Kye, GLOBALFOUNDRIES Inc. (United States)
Harry J. Levinson, GLOBALFOUNDRIES Inc. (United States)

Published in SPIE Proceedings Vol. 7974:
Design for Manufacturability through Design-Process Integration V
Michael L. Rieger, Editor(s)

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