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Proceedings Paper

EUV lithography for 22nm half pitch and beyond: exploring resolution, LWR, and sensitivity tradeoffs
Author(s): E. Steve Putna; Todd R. Younkin; Michael Leeson; Roman Caudillo; Terence Bacuita; Uday Shah; Manish Chandhok
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Paper Abstract

The International Technology Roadmap for Semiconductors (ITRS) denotes Extreme Ultraviolet (EUV) lithography as a leading technology option for realizing the 22nm half pitch node and beyond. According to recent assessments made at the 2010 EUVL Symposium, the readiness of EUV materials remains one of the top risk items for EUV adoption. The main development issue regarding EUV resists has been how to simultaneously achieve high resolution, high sensitivity, and low line width roughness (LWR). This paper describes our strategy, the current status of EUV materials, and the integrated post-development LWR reduction efforts made at Intel Corporation. Data collected utilizing Intel's Micro- Exposure Tool (MET) is presented in order to examine the feasibility of establishing a resist process that simultaneously exhibits ≤22nm half-pitch (HP) L/S resolution at ≤11.3mJ/cm2 with ≤3nm LWR.

Paper Details

Date Published: 8 April 2011
PDF: 9 pages
Proc. SPIE 7969, Extreme Ultraviolet (EUV) Lithography II, 79692K (8 April 2011); doi: 10.1117/12.879641
Show Author Affiliations
E. Steve Putna, Intel Corp. (United States)
Todd R. Younkin, Intel Corp. (United States)
Michael Leeson, Intel Corp. (United States)
Roman Caudillo, Intel Corp. (United States)
Terence Bacuita, Intel Corp. (United States)
Uday Shah, Intel Corp. (United States)
Manish Chandhok, Intel Corp. (United States)


Published in SPIE Proceedings Vol. 7969:
Extreme Ultraviolet (EUV) Lithography II
Bruno M. La Fontaine; Patrick P. Naulleau, Editor(s)

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