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Proceedings Paper

Physical simulation for verification and OPC on full chip level
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Paper Abstract

In this paper, we introduce a rigorous OPC technology that links the physical lithography simulation with the OPC. Firstly, the various aspects of the rigorous OPC, related to process flow, are discussed and the practical feasibility of the embedded rigorous verification is taken into account, which can make the rigorous treatment of the full-chip level possible without any additional manual efforts. We explain an embedded rigorous verification flow and the basic structure of its functionality. Finally, its practical application to real cases is discussed.

Paper Details

Date Published: 5 April 2011
PDF: 9 pages
Proc. SPIE 7973, Optical Microlithography XXIV, 79732I (5 April 2011); doi: 10.1117/12.879577
Show Author Affiliations
Seongbo Shim, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Seongho Moon, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Youngchang Kim, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Seongwoon Choi, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Younghee Kim, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Bernd Küchler, Synopsys GmbH (Germany)
Ulrich Klostermann, Synopsys GmbH (Germany)
Munhoe Do, Synopsys Korea Inc. (Korea, Republic of)
Sooryoung Lee, Synopsys Korea Inc. (Korea, Republic of)


Published in SPIE Proceedings Vol. 7973:
Optical Microlithography XXIV
Mircea V. Dusa, Editor(s)

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