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Proceedings Paper

Layout decomposition of self-aligned double patterning for 2D random logic patterning
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Paper Abstract

Self-aligned double pattering (SADP) has been adapted as a promising solution for sub-30nm technology nodes due to its lower overlay problem and better process tolerance. SADP is in production use for 1D dense patterns with good pitch control such as NAND Flash memory applications, but it is still challenging to apply SADP to 2D random logic patterns. The favored type of SADP for complex logic interconnects is a two mask approach using a core mask and a trim mask. In this paper, we first describe layout decomposition methods of spacer-type double patterning lithography, then report a type of SADP compliant layouts, and finally report SADP applications on Samsung 22nm SRAM layout. For SADP decomposition, we propose several SADP-aware layout coloring algorithms and a method of generating lithography-friendly core mask patterns. Experimental results on 22nm node designs show that our proposed layout decomposition for SADP effectively decomposes any given layouts.

Paper Details

Date Published: 4 April 2011
PDF: 15 pages
Proc. SPIE 7974, Design for Manufacturability through Design-Process Integration V, 79740L (4 April 2011); doi: 10.1117/12.879500
Show Author Affiliations
Yongchan Ban, The Univ. of Texas at Austin (United States)
Alex Miloslavsky, Synopsys, Inc. (United States)
Kevin Lucas, Synopsys, Inc. (United States)
Soo-Han Choi, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Chul-Hong Park, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
David Z. Pan, The Univ. of Texas at Austin (United States)


Published in SPIE Proceedings Vol. 7974:
Design for Manufacturability through Design-Process Integration V
Michael L. Rieger, Editor(s)

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