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Proceedings Paper

Wafer noise models for defect inspection
Author(s): Timothy F. Crimmins
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Paper Abstract

The ability to simulate patterned wafer inspection microscopy is important to guide equipment development, with defect signal-to-noise being the key output metric. With the ongoing introduction of aggressively low k1 lithography, the contribution of wafer noise is becoming one of the dominant noise elements. Quantitative noise models which accurately represent wafer noise are required. The present work develops structural models for line edge roughness and surface roughness. Aerial image FDTD simulations are performed on the model structures and the relationships between the model parameters and defect signal-to-wafer-noise are explored, with conclusions being drawn regarding the wafer inspection sensitivity process window.

Paper Details

Date Published: 20 April 2011
PDF: 6 pages
Proc. SPIE 7971, Metrology, Inspection, and Process Control for Microlithography XXV, 79710E (20 April 2011); doi: 10.1117/12.879477
Show Author Affiliations
Timothy F. Crimmins, Intel Corp. (United States)


Published in SPIE Proceedings Vol. 7971:
Metrology, Inspection, and Process Control for Microlithography XXV
Christopher J. Raymond, Editor(s)

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