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Proceedings Paper

Methodology for overlay mark selection
Author(s): Chin-Chou Kevin Huang; Chao-Tien Healthy Huang; Anna Golotsvan; David Tien; Chui-Fu Chiu; Chun-Yen Huang; Wen-Bin Wu; Chiang-Lin Shih
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Paper Abstract

It is known that different overlay mark designs will have different responses to process setup conditions. An overlay mark optimized for the 45nm technology node might not be suitable for wafers using 30nm or 20nm process technologies due to changes in lithography and process conditions. As overlay control specifications become tighter and tighter, the process engineer requires metrics beyond precision, tool-induced shift (TIS) and TIS variability to determine the optimal target design. In this paper, the authors demonstrate a novel, comprehensive methodology which employs source of variance (SOV) to help engineers select the best overlay marks to meet overlay control requirements.

Paper Details

Date Published: 20 April 2011
PDF: 8 pages
Proc. SPIE 7971, Metrology, Inspection, and Process Control for Microlithography XXV, 79712B (20 April 2011); doi: 10.1117/12.879378
Show Author Affiliations
Chin-Chou Kevin Huang, KLA-Tencor Corp. (United States)
Chao-Tien Healthy Huang, KLA-Tencor Corp. (United States)
Anna Golotsvan, KLA-Tencor Corp. (United States)
David Tien, KLA-Tencor Corp. (United States)
Chui-Fu Chiu, Nanya Technology Corp. (Taiwan)
Chun-Yen Huang, Nanya Technology Corp. (Taiwan)
Wen-Bin Wu, Nanya Technology Corp. (Taiwan)
Chiang-Lin Shih, Nanya Technology Corp. (Taiwan)


Published in SPIE Proceedings Vol. 7971:
Metrology, Inspection, and Process Control for Microlithography XXV
Christopher J. Raymond, Editor(s)

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