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Proceedings Paper

Novel CD-SEM magnification calibration reference of sub-50-nm pitch multi-layer grating with positional identification mark
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Paper Abstract

We fabricated sub-50-nm pitch reference grating with positional identification mark for specifying the location. The address mark of silicon groove was fabricated by EB lithography and dry etching processes. The sub-50-nm pitch multilayer substrate was bonded with the address mark silicon substrate and polished as a flat chip. Next the fine pitch grating reference pattern was fabricated by SiO2 selective chemical etching. Finally the sub-50-nm pitch grating pattern was set on the flat surface for CD-SEM due to retarding bias system for low voltage inspection. As a result of the fundamental characteristics evaluation using CD-SEM, the uniformity of the pitch size in the reference chip was smaller than 1 nm in 3σ. The positional identification marks are useful for obtaining accurate calibrations by specifying the location of the grating and the number of calibrations. Also, the pitch-size was obtained by diffraction angle measurements with a high-accuracy grazing incidence small-angle x-ray scattering (GI-SAXS). The traceability of calibration is under vertification.

Paper Details

Date Published: 20 April 2011
PDF: 9 pages
Proc. SPIE 7971, Metrology, Inspection, and Process Control for Microlithography XXV, 797129 (20 April 2011); doi: 10.1117/12.879347
Show Author Affiliations
Yoshinori Nakayama, Hitachi, Ltd. (Japan)
Jiro Yamamoto, Hitachi, Ltd. (Japan)
Osamu Inoue, Hitachi High-Technologies Corp. (Japan)
Hiroki Kawada, Hitachi High-Technologies Corp. (Japan)
Shozo Yoneda, Hitachi High-Technologies Corp. (Japan)


Published in SPIE Proceedings Vol. 7971:
Metrology, Inspection, and Process Control for Microlithography XXV
Christopher J. Raymond, Editor(s)

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