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Proceedings Paper

Characterization of the performance variation for regular standard cell with process nonidealities
Author(s): Hongbo Zhang; Yuelin Du; Martin D. F. Wong; Kai-Yuan Chao
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Paper Abstract

In IC manufacturing, the performance of standard cells often varies due to process non-idealities. Some research work on 2-D cell characterization shows that the timing variations can be characterized by the timing model. However, as regular design rules become necessary in sub-45nm node circuit design, 1-D design has shown its advantages and has drawn intensive research interest. The circuit performance of a 1-D standard cell can be more accurately predicted than that of a 2-D standard cell as it is insensitive to layout context. This paper presents a characterization methodology to predict the delay and power performance of 1-D standard cells. We perform lithography simulation on the poly gate array generated by dense line printing technology, which constructs the poly gates of inverters, and do statistical analysis on the data simulated within the process window. After that, circuit simulation is performed on the printed cell to obtain its delay and power performance, and the delay and power distribution curves are generated, which accurately predict the circuit performance of standard cells. In the end, the benefits of our cell characterization method are analyzed from both design and manufacturing perspectives, which shows great advantages in accurate circuit analysis and yield improving.

Paper Details

Date Published: 4 April 2011
PDF: 11 pages
Proc. SPIE 7974, Design for Manufacturability through Design-Process Integration V, 79740T (4 April 2011); doi: 10.1117/12.879326
Show Author Affiliations
Hongbo Zhang, Univ. of Illinois at Urbana-Champaign (United States)
Yuelin Du, Univ. of Illinois at Urbana-Champaign (United States)
Martin D. F. Wong, Univ. of Illinois at Urbana-Champaign (United States)
Kai-Yuan Chao, Intel Corp. (United States)

Published in SPIE Proceedings Vol. 7974:
Design for Manufacturability through Design-Process Integration V
Michael L. Rieger, Editor(s)

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