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Proceedings Paper

Accurately predicting copper interconnect topographies in foundry design for manufacturability flows
Author(s): Daniel Lu; Zhong Fan; Ki Duk Tak; Li-Fu Chang; Elain Zou; Jenny Jiang; Josh Yang; Linda Zhuang; Kuang Han Chen; Philippe Hurat; Hua Ding
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Paper Abstract

This paper presents a model-based Chemical Mechanical Polishing (CMP) Design for Manufacturability (DFM) () methodology that includes an accurate prediction of post-CMP copper interconnect topographies at the advanced process technology nodes. Using procedures of extensive model calibration and validation, the CMP process model accurately predicts post-CMP dimensions, such as erosion, dishing, and copper thickness with excellent correlation to silicon measurements. This methodology provides an efficient DFM flow to detect and fix physical manufacturing hotspots related to copper pooling and Depth of Focus (DOF) failures at both block- and full chip level designs. Moreover, the predicted thickness output is used in the CMP-aware RC extraction and Timing analysis flows for better understanding of performance yield and timing impact. In addition, the CMP model can be applied to the verification of model-based dummy fill flows.

Paper Details

Date Published: 4 April 2011
PDF: 8 pages
Proc. SPIE 7974, Design for Manufacturability through Design-Process Integration V, 79740S (4 April 2011); doi: 10.1117/12.879310
Show Author Affiliations
Daniel Lu, Semiconductor Manufacturing International Corp. (China)
Zhong Fan, Semiconductor Manufacturing International Corp. (China)
Ki Duk Tak, Semiconductor Manufacturing International Corp. (China)
Li-Fu Chang, Semiconductor Manufacturing International Corp. (China)
Elain Zou, Semiconductor Manufacturing International Corp. (China)
Jenny Jiang, Semiconductor Manufacturing International Corp. (China)
Josh Yang, Semiconductor Manufacturing International Corp. (China)
Linda Zhuang, Semiconductor Manufacturing International Corp. (China)
Kuang Han Chen, Cadence Design Systems, Inc. (United States)
Philippe Hurat, Cadence Design Systems, Inc. (United States)
Hua Ding, Cadence Design Systems, Inc. (China)


Published in SPIE Proceedings Vol. 7974:
Design for Manufacturability through Design-Process Integration V
Michael L. Rieger, Editor(s)

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