Share Email Print
cover

Proceedings Paper

Litho process control via optimum metrology sampling while providing cycle time reduction and faster metrology-to-litho turn around time
Author(s): K.-H. Chen; Jacky Huang; W.-T. Yang; C.-M. Ke; Y.-C. Ku; John Lin; Kaustuve Bhattacharyya; Evert Mos; Mir Shahrjerdy; Maurits van der Schaar; Steffen Meyer; Spencer Lin; Jon Wu; Sophie Peng; Albert Li; Nikki Chang; Roy Chu; Cathy Wang
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

In keeping up with the tightening overall budget in lithography, metrology requirements have reached a deep subnanometer level [1]. This drives the need for clean metrology (resolution and precision). Results have been published of a thorough investigation of a scatterometry-based platform from ASML [7], showing promising results on resolution, precision, and tool matching for overlay, CD and focus [2 - 6]. But overall requirements are so extreme that all measures must be taken in order to meet them. In light of this, in addition to above-mentioned need for resolution and precision, the speed and sophistication in communication between litho and metrology (feedback control) are also becoming increasingly crucial. An effective sampling strategy for metrology plays a big role in order to achieve this. This study discusses results from above mentioned scatterometry-based platform in light of sampling optimization. For overlay, various sampling schemes (dense / sparse combinations as well as inter and intra field schemes) were used on many production lots. The effectiveness of such sample schemes were studied to reveal an ideal sampling scheme that can result in 0.5nm to 1nm gain in overlay control (compare to today's practice). Moreover, cycle time contribution of metrology (at litho) in overall cycle time of a full process flow was investigated and quantified with the concept of integrated metrology. Results indicate a cycle time reduction per layer (if an integrated concept is used) of 3 to 5 hours, which can easily add up to several days of total cycle time reduction for a fab.

Paper Details

Date Published: 28 March 2011
PDF: 8 pages
Proc. SPIE 7971, Metrology, Inspection, and Process Control for Microlithography XXV, 797105 (28 March 2011); doi: 10.1117/12.879218
Show Author Affiliations
K.-H. Chen, Taiwan Semiconductor Manufacturing Co. Ltd. (Taiwan)
Jacky Huang, Taiwan Semiconductor Manufacturing Co. Ltd. (Taiwan)
W.-T. Yang, Taiwan Semiconductor Manufacturing Co. Ltd. (Taiwan)
C.-M. Ke, Taiwan Semiconductor Manufacturing Co. Ltd. (Taiwan)
Y.-C. Ku, Taiwan Semiconductor Manufacturing Co. Ltd. (Taiwan)
John Lin, Taiwan Semiconductor Manufacturing Co. Ltd. (Taiwan)
Kaustuve Bhattacharyya, ASML Netherlands B.V. (Netherlands)
Evert Mos, ASML Netherlands B.V. (Netherlands)
Mir Shahrjerdy, ASML Netherlands B.V. (Netherlands)
Maurits van der Schaar, ASML Netherlands B.V. (Netherlands)
Steffen Meyer, ASML Netherlands B.V. (Netherlands)
Spencer Lin, ASML Netherlands B.V. (Netherlands)
Jon Wu, ASML Netherlands B.V. (Netherlands)
Sophie Peng, ASML Netherlands B.V. (Netherlands)
Albert Li, ASML Netherlands B.V. (Netherlands)
Nikki Chang, ASML Netherlands B.V. (Netherlands)
Roy Chu, ASML Netherlands B.V. (Netherlands)
Cathy Wang, ASML Netherlands B.V. (Netherlands)


Published in SPIE Proceedings Vol. 7971:
Metrology, Inspection, and Process Control for Microlithography XXV
Christopher J. Raymond, Editor(s)

© SPIE. Terms of Use
Back to Top