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Proceedings Paper

Novel approaches to implement the self-aligned spacer double-patterning process toward 11-nm node and beyond
Author(s): Hidetami Yaegashi; Kenichi Oyama; Kazuo Yabe; Shohei Yamauchi; Arisa Hara; Sakurako Natori
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Paper Abstract

Historically, lithographic scaling has been driven by both improvements in wavelength and numerical aperture. In the semiconductor industry, the transition to 1.35NA immersion lithography has recently been completed, and the focus is now on double patterning techniques (DPT) as a means to circumvent the limitations of Rayleigh's definition. Actually, self-aligned spacer double patterning (SADP) has already been employed in high volume manufacturing of NAND flash memory devices. This paper introduces demonstration results focused on the extendibility of double patterning techniques for various device layouts.

Paper Details

Date Published: 16 April 2011
PDF: 7 pages
Proc. SPIE 7972, Advances in Resist Materials and Processing Technology XXVIII, 79720B (16 April 2011); doi: 10.1117/12.878943
Show Author Affiliations
Hidetami Yaegashi, Tokyo Electron Ltd. (Japan)
Kenichi Oyama, Tokyo Electron Ltd. (Japan)
Kazuo Yabe, Tokyo Electron Ltd. (Japan)
Shohei Yamauchi, Tokyo Electron Ltd. (Japan)
Arisa Hara, Tokyo Electron Ltd. (Japan)
Sakurako Natori, Tokyo Electron Ltd. (Japan)


Published in SPIE Proceedings Vol. 7972:
Advances in Resist Materials and Processing Technology XXVIII
Robert D. Allen; Mark H. Somervell, Editor(s)

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