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Proceedings Paper

Mask enhancer technology with source mask optimization (SMO) for 2Xnm-node logic layout gate fabrication
Author(s): Takashi Matsuda; Shigeo Irie; Tadami Shimizu; Takashi Yuito; Yasuko Tabata; Yuuji Nonami; Akio Misaka; Taichi Koizumi; Masaru Sasago
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Paper Abstract

Strong resolution enhancement technologies (RETs) combined with hyper-NA ArF immersion lithography with source and mask optimization (SMO) have become necessary to achieve sufficient resolution in 2Xnm node devices. Conventional SMO methods have focused on minimizing the edge placement error and/or the cost functions of dose, focus, and mask errors. This has not, however, resolved the conflict between line and gap patterns on logic gate layouts. One issue remaining in particular is the mask error enhancement factor (MEEF). Furthermore, the pattern shapes at the line end gaps of SRAM gates remain a major challenge for logic device manufacturers. To overcome these problems, we explain the importance of controlling the light intensity profiles at line end gaps, focusing on a Panasonic product called "Mask Enhancer" that comprises an attenuated mask with a phase shifting aperture and enables light intensity profiles to be controlled easily. We demonstrate the product's effectiveness in printing gates with optimized illumination source shapes. A simulation experiment and a feasibility study confirmed that Mask Enhancer can improve the MEEF and pattern shapes at the line ends of SRAM gates.

Paper Details

Date Published: 23 March 2011
PDF: 10 pages
Proc. SPIE 7973, Optical Microlithography XXIV, 797316 (23 March 2011); doi: 10.1117/12.878727
Show Author Affiliations
Takashi Matsuda, Panasonic Corp., Semiconductor Co. (Japan)
Shigeo Irie, Panasonic Corp., Semiconductor Co. (Japan)
Tadami Shimizu, Panasonic Corp., Semiconductor Co. (Japan)
Takashi Yuito, Panasonic Corp., Semiconductor Co. (Japan)
Yasuko Tabata, Panasonic Corp., Semiconductor Co. (Japan)
Yuuji Nonami, Panasonic Corp., Semiconductor Co. (Japan)
Akio Misaka, Panasonic Corp., Semiconductor Co. (Japan)
Taichi Koizumi, Panasonic Corp., Semiconductor Co. (Japan)
Masaru Sasago, Panasonic Corp., Semiconductor Co. (Japan)


Published in SPIE Proceedings Vol. 7973:
Optical Microlithography XXIV
Mircea V. Dusa, Editor(s)

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