Share Email Print
cover

Proceedings Paper

Applying litho-aware timing analysis to hold time fixing reduces design cycle time and power dissipation
Author(s): Keisuke Hirabayashi; Naohiro Kobayashi; Hidemichi Mizuno; Tomoo Onodera; Tsuyoshi Oguro; Philippe Hurat; Arindam Chatterjee; Koichi Seki
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

In this paper, we present an innovative approach to reduce power and accelerate timing closure by using simulated silicon-calibrated contours to predict the litho effects on transistor gates and perform litho-aware critical paths analysis. This approach is used to filter the false hold time violations and focus designers' actions on the most relevant violations. After silicon validation, the application of this technique to hold time fixing on a 90nm micro-controller unit product reduces the power increase and runtime of the hold buffer insertion. This study not only demonstrates the feasibility of the Litho-aware STA flow but also shows its value to reduce hold time fixing effort and power dissipation caused by buffer insertion.

Paper Details

Date Published: 4 April 2011
PDF: 10 pages
Proc. SPIE 7974, Design for Manufacturability through Design-Process Integration V, 797408 (4 April 2011); doi: 10.1117/12.878695
Show Author Affiliations
Keisuke Hirabayashi, Renesas Electronics Corp. (Japan)
Naohiro Kobayashi, Renesas Electronics Corp. (Japan)
Hidemichi Mizuno, Renesas Electronics Corp. (Japan)
Tomoo Onodera, Renesas Electronics Corp. (Japan)
Tsuyoshi Oguro, Renesas Electronics Corp. (Japan)
Philippe Hurat, Cadence Design Systems, Inc. (United States)
Arindam Chatterjee, Cadence Design Systems, Inc. (United States)
Koichi Seki, Cadence Design Systems, Japan B.V. (Japan)


Published in SPIE Proceedings Vol. 7974:
Design for Manufacturability through Design-Process Integration V
Michael L. Rieger, Editor(s)

© SPIE. Terms of Use
Back to Top