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Proceedings Paper

CD correction for half pitch 2x-nm on extreme ultraviolet lithography
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Paper Abstract

This paper describes the critical dimension (CD) accuracy of metal-layer patterns for the 15-nm logic node and beyond replicated with model-based optical proximity correction, flare variation compensation, and shadowing effect correction. The model fitting took resist shrinkage during CD measurements into account so as to reduce the modeling error. Since sufficient accuracy was obtained for various patterns under the assumptions of device production, and since conventional illumination could be used, it was possible to establish a design rule with few restrictions for the 15-nm node. For the 12-nm logic node, an SRAM pattern for a cell size of 0.0288 μm2 was fabricated using dipole illumination. Advanced pre-production optics were used to assess the impact of flare on CD variation. Since chemical flare occurs in SSR4, a top coating was used to prevent acid re-adsorption during the post-exposure bake. The flare due to the optics was reduced to half that of conventional optics, and the CD variation due to flare was found to be predictable from the point spread function of the projection optics. This means that the established concept of flare correction is usable with advanced optics.

Paper Details

Date Published: 7 April 2011
PDF: 12 pages
Proc. SPIE 7969, Extreme Ultraviolet (EUV) Lithography II, 79691J (7 April 2011); doi: 10.1117/12.878672
Show Author Affiliations
Hajime Aoyama, Semiconductor Leading Edge Technologies, Inc. (Japan)
Yuusuke Tanaka, Semiconductor Leading Edge Technologies, Inc. (Japan)
Kazuo Tawarayama, Semiconductor Leading Edge Technologies, Inc. (Japan)
Yukiyasu Arisawa, Semiconductor Leading Edge Technologies, Inc. (Japan)
Taiga Uno, Semiconductor Leading Edge Technologies, Inc. (Japan)
Takashi Kamo, Semiconductor Leading Edge Technologies, Inc. (Japan)
Toshihiko Tanaka, Semiconductor Leading Edge Technologies, Inc. (Japan)
Alan Myers, Intel Corp. (United States)
Yashesh Shroff, Intel Corp. (United States)
Tetsunori Murachi, Intel Corp. (United States)
Gilroy Vandentop, Intel Corp. (United States)
Ichiro Mori, Semiconductor Leading Edge Technologies, Inc. (Japan)


Published in SPIE Proceedings Vol. 7969:
Extreme Ultraviolet (EUV) Lithography II
Bruno M. La Fontaine; Patrick P. Naulleau, Editor(s)

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