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Proceedings Paper

Extending analog design scaling to sub-wavelength lithography: co-optimization of RET and photomasks
Author(s): Ashesh Parikh; Siew Dorris; Tom Smelko; Walter Walbrick; Pushpa Mahalingam; John Arch; Kent Green; Vishal Garg; Peter Buck; Craig West
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Paper Abstract

The mask requirements for 110nm half-node BiCMOS process were analyzed with the goal to meet customer needs at lower cost and shorter cycle times. The key differentiating features for this technology were high density CMOS libraries along with high-power Bipolar, LDMOS and DECMOS components. The high voltage components were characterized by transistors that formed cylindrical junctions. The presence of curved features in the data is particularly detrimental to the write time on a 50KeV vector mask writer. The mask write times have a direct impact on both mask cost and cycle time. Design rules also permit rectangular or stretched contacts to allow conductance of high currents. To meet customer needs but still manage the computational lithography overhead as well as the patterning process performance, this process was evaluated in terms of computational lithography and photomask co-optimization for the base-line 50KeV vector and laser mask-writers. Due to the differences in imaging and processing of the different mask writing systems, comparative analysis of critical dimension (CD) performance both in terms of linearity and pitch was done. Differences in imaging on silicon due to mask fidelity were also expected and characterized. The required changes in OPC necessary to switch to the new mask process were analyzed.

Paper Details

Date Published: 4 April 2011
PDF: 8 pages
Proc. SPIE 7974, Design for Manufacturability through Design-Process Integration V, 79740N (4 April 2011); doi: 10.1117/12.877487
Show Author Affiliations
Ashesh Parikh, Texas Instruments Inc. (United States)
Siew Dorris, Texas Instruments Inc. (United States)
Tom Smelko, Texas Instruments Inc. (United States)
Walter Walbrick, Texas Instruments Inc. (United States)
Pushpa Mahalingam, Texas Instruments Inc. (United States)
John Arch, Texas Instruments Inc. (United States)
Kent Green, Toppan Photomasks, Inc. (United States)
Vishal Garg, Toppan Photomasks, Inc. (United States)
Peter Buck, Toppan Photomasks, Inc. (United States)
Craig West, Toppan Photomasks, Inc. (United States)

Published in SPIE Proceedings Vol. 7974:
Design for Manufacturability through Design-Process Integration V
Michael L. Rieger, Editor(s)

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