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Proceedings Paper

Design and fabrication of a CMOS MEMS logic gate
Author(s): Chun-Yin Tsai; Tsung-Lin Chen; Hsin-Hao Liao; Chen-Fu Lin; Ying-Zong Juang
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Paper Abstract

This study aims to develop a novel CMOS-MEMS logic gate via commercially available CMOS process (TSMC, 2P4M®). Compared to existing CMOS MEMS designs, which uses foundry processes, the proposed design imposes several new challenges including: carrying two voltage levels on a non-warping suspended plate, metal-to- metal contact, and etc. Different combinations of oxide-metal films and post-CMOS process are investigated to achieve a non-warping suspended structure layer. And different wet etchants are investigated to remove sacrificial layers without attacking structure layers and features. In a prototype design, the selected structure layer is metal-3 and oxide film; the device is released using AD-10 and titanium etchant; the device is 250 μm long, 100 μm wide, and 1.5 μm gap. The experimental results show that the suspended plate slightly curls down 0.485 μm. This device can be actuated by 10/0 V with a moving distance 50nm. The resonant frequency is measured at 36 kHz. Due to the damage of the tungsten plugs, the logic function can only be verified by its mechanical movements instead of electrical readouts for now.

Paper Details

Date Published: 15 February 2011
PDF: 13 pages
Proc. SPIE 7926, Micromachining and Microfabrication Process Technology XVI, 79260I (15 February 2011); doi: 10.1117/12.874341
Show Author Affiliations
Chun-Yin Tsai, National Chiao Tung Univ. (Taiwan)
Tsung-Lin Chen, National Chiao Tung Univ. (Taiwan)
Hsin-Hao Liao, National Chip Implementation Ctr. (Taiwan)
Chen-Fu Lin, National Chip Implementation Ctr. (Taiwan)
Ying-Zong Juang, National Chip Implementation Ctr. (Taiwan)


Published in SPIE Proceedings Vol. 7926:
Micromachining and Microfabrication Process Technology XVI
Mary Ann Maher; Jung-Chih Chiao; Paul J. Resnick, Editor(s)

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