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Proceedings Paper

An analog logarithmic number system subtractor for edge detection in logarithmic CMOS image sensors
Author(s): D. R. Desai; F. H. Hassan; R. J. Veillette; J. E. Carletta
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Paper Abstract

This paper describes the design of analog circuitry to implement logarithmic number system (LNS) subtraction. Such circuitry, if incorporated in the readout circuitry of a logarithmic CMOS image sensor, would allow for the on-chip calculation of spatial derivatives, while operating directly on logarithmically-scaled pixels. The circuit was implemented for a 1.2μm CMOS process. The maximum relative error at the output of the LNS subtractor for pixel currents that correspond to an illumination range of more than four decades is 4.26%.

Paper Details

Date Published: 16 February 2011
PDF: 7 pages
Proc. SPIE 7875, Sensors, Cameras, and Systems for Industrial, Scientific, and Consumer Applications XII, 78750C (16 February 2011); doi: 10.1117/12.872461
Show Author Affiliations
D. R. Desai, The Univ. of Akron (United States)
F. H. Hassan, Ohio Northern Univ. (United States)
R. J. Veillette, The Univ. of Akron (United States)
J. E. Carletta, The Univ. of Akron (United States)


Published in SPIE Proceedings Vol. 7875:
Sensors, Cameras, and Systems for Industrial, Scientific, and Consumer Applications XII
Ralf Widenhorn; Valérie Nguyen, Editor(s)

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