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Proceedings Paper

Acceleration of feature extraction for FPGA-based speech recognition
Author(s): Vytautas Arminas; Gintautas Tamulevicius; Dalius Navakauskas; Edgaras Ivanovas
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Paper Abstract

The paper describes a field programmable gate array implementation of the main part of speech recognition system - feature extraction. In order to accelerate recognition the whole cepstral analysis scheme is implemented in hardware by the use of intellectual property cores. Two field programmable gate array devices are used for evaluation. Comparative experimental results of four different implementations are presented. They grounds achieved 29 times faster speech analysis in comparison with software based analysis subsystem.

Paper Details

Date Published: 14 September 2010
PDF: 6 pages
Proc. SPIE 7745, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2010, 774511 (14 September 2010); doi: 10.1117/12.872081
Show Author Affiliations
Vytautas Arminas, Vilnius Gediminas Technical Univ. (Lithuania)
Gintautas Tamulevicius, Institute of Mathematics and Informatics (Lithuania)
Dalius Navakauskas, Vilnius Gediminas Technical Univ. (Lithuania)
Edgaras Ivanovas, Vilnius Gediminas Technical Univ. (Lithuania)


Published in SPIE Proceedings Vol. 7745:
Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2010
Ryszard S. Romaniuk, Editor(s)

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