Share Email Print
cover

Proceedings Paper

Statistical approach to specify DPT process in terms of patterning and electrical performance of sub-30nm DRAM device
Author(s): Yu-Jin Pyo; Soo-Han Choi; Chul-Hong Park; Sang-Hoon Lee; Moon-Hyun Yoo; Gyu-Tae Kim
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

Double-patterning technology (DPT) has been a primary lithography candidate of the sub-30nm technology node. The major concern of DPT is the critical dimension (CD) skew and overlay error between 1st and 2nd patterning, which cause the degradation of the electrical performance in terms of timing delay. In this paper, we newly develop a systematic method to determine the DPT scheme and the proper process specification using a statistical approach in perspective of the pattering and electrical performance. Applying the method to the bit-line layer of the sub-30nm DRAM device, we determine the DPT scheme (i.e. either litho-etch-litho-etch (LELE) or self-aligned double pattering (SADP) to avoid the patterning hotspots. In addition, analyzing the statistical simulation result, we provide the process specification and exposing sequence of two masks to avoid the electrical degradation.

Paper Details

Date Published: 5 April 2011
PDF: 7 pages
Proc. SPIE 7974, Design for Manufacturability through Design-Process Integration V, 797413 (5 April 2011); doi: 10.1117/12.869978
Show Author Affiliations
Yu-Jin Pyo, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Soo-Han Choi, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Korea Univ. (Korea, Republic of)
Chul-Hong Park, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Sang-Hoon Lee, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Moon-Hyun Yoo, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Gyu-Tae Kim, Korea Univ. (Korea, Republic of)


Published in SPIE Proceedings Vol. 7974:
Design for Manufacturability through Design-Process Integration V
Michael L. Rieger, Editor(s)

© SPIE. Terms of Use
Back to Top