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Proceedings Paper

Affordable and process window increasing full chip ILT masks
Author(s): Guangming Xiao; Dave Irby; Tom Cecil; David Kim; Shuichiro Ohara; Isao Aburatani
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Paper Abstract

To enable Inverse Lithography Technology (ILT) for production as one of the leading candidates for low-k1 lithography at 32nm and below, one major task to overcome is mask manufacturability including mask data fracturing, MRC constraints, writing time, and inspection. In prior publications[1,2], it has been shown that the Inverse Synthesizer (ISTM) produces ILT full chip mask of contact layer with comparable mask write time with conventional OPC while maintaining the significant litho gains of ILT mask. To fully integrate ILT masks into production for all layers including line and space layers such as poly layer, a number of areas were investigated to further reduce ILT mask complexity and total e-beam shot count. These areas include flexible controls of SRAF placements with respect to local feature sizes, improved Manhattan algorithm, topology based variable Manhattan segmentation, jog alignment and mask data fracture optimization. The impact of these approaches on e-beam shot count and lithography performance of ILT masks is presented in the paper.

Paper Details

Date Published: 29 September 2010
PDF: 12 pages
Proc. SPIE 7823, Photomask Technology 2010, 78233T (29 September 2010); doi: 10.1117/12.866131
Show Author Affiliations
Guangming Xiao, Luminescent Technologies, Inc. (United States)
Dave Irby, Luminescent Technologies, Inc. (United States)
Tom Cecil, Luminescent Technologies, Inc. (United States)
David Kim, Luminescent Technologies, Inc. (United States)
Shuichiro Ohara, Nippon Control System Corp. (Japan)
Isao Aburatani, Nippon Control System Corp. (Japan)

Published in SPIE Proceedings Vol. 7823:
Photomask Technology 2010
M. Warren Montgomery; Wilhelm Maurer, Editor(s)

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