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Proceedings Paper

EUV mask defect mitigation through pattern placement
Author(s): John Burns; Mansoor Abbas
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Paper Abstract

One of the challenges of EUVL is to bring EUV mask blank defect levels to zero. With uncertainty on when defect free masks may be routinely available, we explore a possibility for effectively using defective EUV mask blanks in production with a defect avoidance strategy. The key idea is to position the pattern/layout on the blank where the defects do not impact the final wafer image. Assuming that layout designs contain some non-critical areas in which defects can be safely positioned, it may be possible to align these regions with a given, small set of defect positions mapped from an imperfect mask blank. Using a few representative assortment of current-node, full-chip layout patterns we run multiple trials against real blank defect maps with various defect counts successfully. Our goal is to assess the probabilities that defect avoidance will work as a function of mask blank defect count, and by lithography layer.

Paper Details

Date Published: 25 September 2010
PDF: 5 pages
Proc. SPIE 7823, Photomask Technology 2010, 782340 (25 September 2010); doi: 10.1117/12.865160
Show Author Affiliations
John Burns, Synopsys, Inc. (United States)
Mansoor Abbas, Synopsys, Inc. (United States)


Published in SPIE Proceedings Vol. 7823:
Photomask Technology 2010
M. Warren Montgomery; Wilhelm Maurer, Editor(s)

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