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Proceedings Paper

A novel VLSI architecture of arithmetic encoder with reduced memory in SPIHT
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Paper Abstract

The paper presents a context-based arithmetic coder's VLSI architecture used in SPIHT with reduced memory, which is used for high speed real-time applications. For hardware implementation, a dedicated context model is proposed for the coder. Each context can be processed in parallel and high speed operators are used for interval calculations. An embedded register array is used for cumulative frequency update. As a result, the coder can consume one symbol at each clock cycle. After FPGA synthesis and simulation, the throughput of our coder is comparable with those of similar hardware architectures used in ASIC technology. Especially, the memory capacity of the coder is smaller than those of corresponding systems.

Paper Details

Date Published: 24 August 2010
PDF: 8 pages
Proc. SPIE 7810, Satellite Data Compression, Communications, and Processing VI, 78100L (24 August 2010); doi: 10.1117/12.860273
Show Author Affiliations
Kai Liu, Xidian Univ. (China)
YunSong Li, Xidian Univ. (China)
Eugeniy Belyaev, Saint-Petersburg Institute for Informatics and Automation (Russian Federation)


Published in SPIE Proceedings Vol. 7810:
Satellite Data Compression, Communications, and Processing VI
Bormin Huang; Antonio J. Plaza; Joan Serra-Sagristà; Chulhee Lee; Yunsong Li; Shen-En Qian, Editor(s)

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