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Proceedings Paper

Method to implement the CCD timing generator based on FPGA
Author(s): Binhua Li; Qian Song; Chun He; Jianhui Jin; Lin He
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Paper Abstract

With the advance of the PFPA technology, the design methodology of digital systems is changing. In recent years we develop a method to implement the CCD timing generator based on FPGA and VHDL. This paper presents the principles and implementation skills of the method. Taking a developed camera as an example, we introduce the structure, input and output clocks/signals of a timing generator implemented in the camera. The generator is composed of a top module and a bottom module. The bottom one is made up of 4 sub-modules which correspond to 4 different operation modes. The modules are implemented by 5 VHDL programs. Frame charts of the architecture of these programs are shown in the paper. We also describe implementation steps of the timing generator in Quartus II, and the interconnections between the generator and a Nios soft core processor which is the controller of this generator. Some test results are presented in the end.

Paper Details

Date Published: 20 July 2010
PDF: 9 pages
Proc. SPIE 7742, High Energy, Optical, and Infrared Detectors for Astronomy IV, 77421Y (20 July 2010); doi: 10.1117/12.858196
Show Author Affiliations
Binhua Li, Kunming Univ. of Science and Technology (China)
Qian Song, National Astronomical Observatories (China)
Chun He, Kunming Univ. of Science and Technology (China)
Jianhui Jin, Kunming Univ. of Science and Technology (China)
Lin He, Kunming Univ. of Science and Technology (China)


Published in SPIE Proceedings Vol. 7742:
High Energy, Optical, and Infrared Detectors for Astronomy IV
Andrew D. Holland; David A. Dorn, Editor(s)

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