Share Email Print
cover

Proceedings Paper

Accelerating the dual damascene process time by new filling material
Author(s): Kung-Hsun Tsao; Yu-Huan Liu; Tsz-Yuan Chen; Chih-Jung Chen; C. C. Huang; Yung-Cheng Chang; Go Noya; Nick Hsiao; Simon Chiu; Vencent Chang; Tomohide Katayama; Hisashi Motobayashi
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Dual damascene technique has been widely applied to IC device fabrication in copper interconnect process. For traditional via-first dual damascene application, a fill material is first employed to fill via to protect over-etching and punch-through of the bottom barrier layer during the trench-etch process. Etch-back process is then applied to remove excess overfill thickness and maintain a greater planar topography. To get better CD control, a thin organic BARC is finally coated to reduce reflectivity for trench patterning but not in this study. It is a multi-step and costly dual damascene process. In this study, a new gap-filling BARC material with good via fill and light absorption features was adopted to explore the via-first dual damascene process by skipping etch-back and BARC coating steps. The results show not only the reduction of process cycle time and cost saving but also the CP yield improvement based on data from pilot production of 0.11/0.13 μm logic device.

Paper Details

Date Published: 30 March 2010
PDF: 10 pages
Proc. SPIE 7639, Advances in Resist Materials and Processing Technology XXVII, 76392A (30 March 2010); doi: 10.1117/12.855997
Show Author Affiliations
Kung-Hsun Tsao, United Microelectronics Corp. (Taiwan)
Yu-Huan Liu, United Microelectronics Corp. (Taiwan)
Tsz-Yuan Chen, United Microelectronics Corp. (Taiwan)
Chih-Jung Chen, United Microelectronics Corp. (Taiwan)
C. C. Huang, United Microelectronics Corp. (Taiwan)
Yung-Cheng Chang, AZ Electronic Materials Taiwan Co., Ltd. (Taiwan)
Go Noya, AZ Electronic Materials Taiwan Co., Ltd. (Taiwan)
Nick Hsiao, AZ Electronic Materials Taiwan Co., Ltd. (Taiwan)
Simon Chiu, AZ Electronic Materials Taiwan Co., Ltd. (Taiwan)
Vencent Chang, AZ Electronic Materials Taiwan Co., Ltd. (Taiwan)
Tomohide Katayama, AZ Electronic Materials K.K. (Japan)
Hisashi Motobayashi, AZ Electronic Materials K.K. (Japan)


Published in SPIE Proceedings Vol. 7639:
Advances in Resist Materials and Processing Technology XXVII
Robert D. Allen, Editor(s)

© SPIE. Terms of Use
Back to Top