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Proceedings Paper

A 3D chip architecture for optical sensing and concurrent processing
Author(s): Ángel Rodríguez-Vázquez; Ricardo Carmona; Carlos Domínguez Matas; Manuel Suárez-Cambre; Victor Brea; Francisco Pozas; Gustavo Liñán; Peter Foldessy; Akos Zarandy; Csaba Rekeczky
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Paper Abstract

This paper presents an architecture for the implementation of vision chips in 3-D integration technologies. This architecture employs the multi-functional pixel concept to achieve full parallel processing of the information and hence high processing speed. The top layer includes an array of optical sensors which are parallel-connected to the second layer, consisting of an array of mixed-signal read-out and pre-processing cells. Multiplexing is employed so that each mixedsignal cell handles several optical sensors. The two remaining layer are respectively a memory (used to store different multi-scale images obtained at the mixed-signal layer) and an array of digital processors. A prototype of this architecture has been implemented in a FDSOI CMOS-3D technology with Through-Silicon-Vias of 5μm x 5μm pitch.

Paper Details

Date Published: 14 May 2010
PDF: 12 pages
Proc. SPIE 7726, Optical Sensing and Detection, 772613 (14 May 2010); doi: 10.1117/12.855027
Show Author Affiliations
Ángel Rodríguez-Vázquez, IMSE-CNM/CSIC and Univ. Sevilla (Spain)
Innovaciones Microelectrónicas S.L. (Spain)
Ricardo Carmona, IMSE-CNM/CSIC and Univ. Sevilla (Spain)
Carlos Domínguez Matas, Innovaciones Microelectrónicas S.L. (Spain)
Manuel Suárez-Cambre, Univ. de Santiago de Compostela (Spain)
Victor Brea, Univ. de Santiago de Compostela (Spain)
Francisco Pozas, IMSE-CNM/CSIC and Univ. Sevilla (Spain)
Gustavo Liñán, IMSE-CNM/CSIC and Univ. Sevilla (Spain)
Peter Foldessy, MTA-SZTAKI (Hungary)
Akos Zarandy, MTA-SZTAKI (Hungary)
Csaba Rekeczky, Eutecus Inc. (United States)

Published in SPIE Proceedings Vol. 7726:
Optical Sensing and Detection
Francis Berghmans; Anna Grazia Mignani; Chris A. van Hoof, Editor(s)

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