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Proceedings Paper

A 10Gb/s transimpedance amplifier for hybrid integration of a Ge PIN waveguide photodiode
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Paper Abstract

The presented paper describes a 10 Gbps optical receiver. The transimpedance amplifier (TIA) is realized in standard 0.35 μm SiGe BiCMOS technology. The main novelty of the presented design - investigated in the European Community project HELIOS - is the hybrid connection of the optical detector. The used Germanium photodetector will be directly mounted onto the receiver. A model of the relevant parasitics of the photodetector itself and the novel connection elements (micropads, metal vias and metal lines) is described. Based on this photodetector model an optical receiver circuit was optimized for maximum sensitivity at data rates in the range of 10 Gbps. The design combines a TIA and two limiting amplifier stages followed by a 50 Ω CML-style logic-level output driver. To minimize power supply noise and substrate noise, a fully differential design is used. A dummy TIA provides a symmetrical input signal reference and a control loop is used to compensate the offset levels. The TIA is built around a common-emitter stage and features a feedback resistor of 4.2 Ω. The total transimpedance of the complete receiver chain is in the range of 275 kΩ. The value of the active feedback resistor can be reduced via an external control voltage to adapt the design to different overall gain requirements. The two limiting amplifier stages are realized as differential amplifiers with voltage followers. The output buffer is implemented with cascode differential amplifiers. The output buffer is capable of driving a differential 50Ω output with a calculated output swing of 800mVp-p. Simulations show an overall bandwidth of 7.2 GHz. The lower cutoff frequency is below 60 kHz. The equivalent input noise current is 408 nA. With an estimated total photodiode responsivity of 0.5 A/W this allows a sensitivity of around - 23.1 dBm (BER = 10-9). The device operates from a single 3.3 V power supply and the TIAs and the limiting amplifier consume 32 mA.

Paper Details

Date Published: 18 May 2010
PDF: 9 pages
Proc. SPIE 7719, Silicon Photonics and Photonic Integrated Circuits II, 77191N (18 May 2010); doi: 10.1117/12.854312
Show Author Affiliations
A. Polzer, Technische Univ. Wien (Austria)
W. Gaberl, Technische Univ. Wien (Austria)
R. Swoboda, Technische Univ. Wien (Austria)
H. Zimmermann, Technische Univ. Wien (Austria)
J.-M. Fedeli, CEA, LETI, Minatec (France)
L. Vivien, Institut d'Electronique Fondamentale, CNRS, Univ. Paris-Sud XI (France)


Published in SPIE Proceedings Vol. 7719:
Silicon Photonics and Photonic Integrated Circuits II
Giancarlo Cesare Righini, Editor(s)

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