Share Email Print
cover

Proceedings Paper

Line width roughness effects on device performance: the role of the gate width design
Author(s): V. Constantoudis; E. Gogolides; G. P. Patsis
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

The role of the gate width in the effects of Line Width Roughness (LWR) on transistor performance is investigated. Two mathematical results regarding the statistical nature of LWR are presented and discussed. The implications of these results on the effects of LWR on transistor performance are investigated through a 2D modeling approach. It is found that, for fixed LWR induced by manufacturing processes, transistors designed with large gate widths seem to mitigate the degradation effects of LWR on transistor performance.

Paper Details

Date Published: 3 April 2010
PDF: 8 pages
Proc. SPIE 7641, Design for Manufacturability through Design-Process Integration IV, 764116 (3 April 2010); doi: 10.1117/12.853317
Show Author Affiliations
V. Constantoudis, National Ctr. for Scientific Research Demokritos (Greece)
E. Gogolides, National Ctr. for Scientific Research Demokritos (Greece)
G. P. Patsis, National Ctr. for Scientific Research Demokritos (Greece)


Published in SPIE Proceedings Vol. 7641:
Design for Manufacturability through Design-Process Integration IV
Michael L. Rieger; Joerg Thiele, Editor(s)

© SPIE. Terms of Use
Back to Top