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Proceedings Paper

Exploiting current-generation graphics hardware for synthetic-scene generation
Author(s): Michael A. Tanner; Wayne A. Keen
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Paper Abstract

Increasing seeker frame rate and pixel count, as well as the demand for higher levels of scene fidelity, have driven scene generation software for hardware-in-the-loop (HWIL) and software-in-the-loop (SWIL) testing to higher levels of parallelization. Because modern PC graphics cards provide multiple computational cores (240 shader cores for a current NVIDIA Corporation GeForce and Quadro cards), implementation of phenomenology codes on graphics processing units (GPUs) offers significant potential for simultaneous enhancement of simulation frame rate and fidelity. To take advantage of this potential requires algorithm implementation that is structured to minimize data transfers between the central processing unit (CPU) and the GPU. In this paper, preliminary methodologies developed at the Kinetic Hardware In-The-Loop Simulator (KHILS) will be presented. Included in this paper will be various language tradeoffs between conventional shader programming, Compute Unified Device Architecture (CUDA) and Open Computing Language (OpenCL), including performance trades and possible pathways for future tool development.

Paper Details

Date Published: 24 April 2010
PDF: 9 pages
Proc. SPIE 7663, Technologies for Synthetic Environments: Hardware-in-the-Loop Testing XV, 76630P (24 April 2010); doi: 10.1117/12.851798
Show Author Affiliations
Michael A. Tanner, Air Force Research Lab. (United States)
Wayne A. Keen, L3 GS&ES (United States)


Published in SPIE Proceedings Vol. 7663:
Technologies for Synthetic Environments: Hardware-in-the-Loop Testing XV
James A. Buford; Robert Lee Murrer, Editor(s)

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