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Proceedings Paper

Nios II hardware acceleration of the epsilon quadratic sieve algorithm
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Paper Abstract

The quadratic sieve (QS) algorithm is one of the most powerful algorithms to factor large composite primes used to break RSA cryptographic systems. The hardware structure of the QS algorithm seems to be a good fit for FPGA acceleration. Our new ε-QS algorithm further simplifies the hardware architecture making it an even better candidate for C2H acceleration. This paper shows our design results in FPGA resource and performance when implementing very long arithmetic on the Nios microprocessor platform with C2H acceleration for different libraries (GMP, LIP, FLINT, NRMP) and QS architecture choices for factoring 32-2048 bit RSA numbers.

Paper Details

Date Published: 12 April 2010
PDF: 10 pages
Proc. SPIE 7703, Independent Component Analyses, Wavelets, Neural Networks, Biosystems, and Nanoengineering VIII, 77030M (12 April 2010); doi: 10.1117/12.849883
Show Author Affiliations
Uwe Meyer-Bäse, Florida State Univ. (United States)
Guillermo Botella, Florida State Univ. (United States)
Encarnacion Castillo, Univ. of Granada (Spain)
Antonio García, Univ. of Granada (Spain)


Published in SPIE Proceedings Vol. 7703:
Independent Component Analyses, Wavelets, Neural Networks, Biosystems, and Nanoengineering VIII
Harold H. Szu; F. Jack Agee, Editor(s)

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