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Proceedings Paper

Measurement and optimization of electrical process window
Author(s): Tuck-Boon Chan; Abde Ali Kagalwalla; Puneet Gupta
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Paper Abstract

Process window (PW) is a collection of values of process parameters that allow circuit to be printed and to operate under desired specifications. Conventional process window which is determined through geometrical fidelity, geometric process window (GPW), does not account for lithography effects on electrical metrics such as delay and power. In contrast to GPW, this paper introduces electrical process window (EPW) which accounts for electrical specifications. Process parameters are considered within EPW if the performance (delay and leakage power) of printed circuit is within desired specifications. Our experiment results show that the area of EPW is 1.5~6x larger than that of GPW. This implies that even if a layout falls outside geometric tolerance, the electrical performance of the circuit may satisfy desired specifications. In addition to process window evaluation, we show that EPW can be enlarged by 10% on average using gate length biasing and Vth push. We also propose approximate methods to evaluate EPW, which can be used in the absence of any design information. Our results show that the proposed approximation method can estimate more than 80% of the area of reference EPW.

Paper Details

Date Published: 3 April 2010
PDF: 11 pages
Proc. SPIE 7641, Design for Manufacturability through Design-Process Integration IV, 76410J (3 April 2010); doi: 10.1117/12.849066
Show Author Affiliations
Tuck-Boon Chan, Univ. of California, Los Angeles (United States)
Abde Ali Kagalwalla, Univ. of California, Los Angeles (United States)
Puneet Gupta, Univ. of California, Los Angeles (United States)


Published in SPIE Proceedings Vol. 7641:
Design for Manufacturability through Design-Process Integration IV
Michael L. Rieger; Joerg Thiele, Editor(s)

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