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Proceedings Paper

Tracking of design related defects hidden by random defectivity in production environment
Author(s): J. C. Le Denmat; V. Charbois; L. Tetar; M. C. Luche; G. Kerrien; F. Robert; E. Yesilada; F. Foussadier; L. Couturier; L. Karsenti; M. Geshel
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Paper Abstract

For mature technology nodes, main yield detractor is random defectivity. Nevertheless, some devices can show higher defectivity than rest of devices. Out of process accident, design related defect is one of suspected root cause. Also, design-based defect category is expected to increase as technology node decreases. Determining origin of these additional systematic defects is not easy as these defects are usually residual for technologies in production, not always predictable by OPC simulator (ex: void defect in active STI structure), and at least hidden by random defectivity after in-line wafer inspection control. In this paper, an automatic flow to track systematic defects within global defectivity is presented. This flow starts with a relevant selection of several inspection defect files for a given device. Then the Design Based Binning (DBB) tool performs a fine alignment of the whole multi wafer inspection data set with design file. The resulting aligned defect file is treated by an efficient pattern matching algorithm to generate a design-based binning (DBB) defect file. The integration of this output defect file into a Yield Management System (YMS) allows easy defect analysis and statistical correlation to electrical results. An example of design-based defects tracking analysis and their impact on yield of a mature technology node device is presented in this paper.

Paper Details

Date Published: 3 April 2010
PDF: 9 pages
Proc. SPIE 7641, Design for Manufacturability through Design-Process Integration IV, 76410Y (3 April 2010); doi: 10.1117/12.848763
Show Author Affiliations
J. C. Le Denmat, STMicroelectronics (France)
V. Charbois, STMicroelectronics (France)
L. Tetar, STMicroelectronics (France)
M. C. Luche, STMicroelectronics (France)
G. Kerrien, STMicroelectronics (France)
F. Robert, STMicroelectronics (France)
E. Yesilada, STMicroelectronics (France)
F. Foussadier, STMicroelectronics (France)
L. Couturier, Applied Materials France (France)
L. Karsenti, Applied Materials Israel (Israel)
M. Geshel, Applied Materials Israel (Israel)


Published in SPIE Proceedings Vol. 7641:
Design for Manufacturability through Design-Process Integration IV
Michael L. Rieger; Joerg Thiele, Editor(s)

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