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Proceedings Paper

Process variation monitoring (PVM) by wafer inspection tool as a complementary method to CD-SEM for mapping field CDU on advanced production devices
Author(s): Dae Jong Kim; Hyung Won Yoo; Chul Hong Kim; Hak Kwon Lee; Sung Su Kim; Koon Ho Bae; Hedvi Spielberg; Yun Ho Lee; Shimon Levi; Yariv Bustan; Moshe Rozentsvige
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Paper Abstract

As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) have a dramatic effect on printed final lines and hence the need to control these parameters increases. Sources of CDU and LER variations include scanner auto-focus accuracy and stability, layer stack thickness, composition variations, and exposure variations. Process variations, in advanced VLSI production designs, specifically in memory devices, attributed to CDU and LER affect cell-to-cell parametric variations. These variations significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or OCD metrology tools. Typically, these measurements require a relatively long time to set and cover only selected points of wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials and Hynix Semiconductor Inc. on the implementation of a complementary method to the CDSEM and OCD tools, to monitor defect density and post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM) is based on measuring variations in the scattered light from periodic structures. The application is demonstrated using Applied Materials DUV bright field (BF) wafer inspection tool under optimized illumination and collection conditions. The UVisionTM has already passed a successful feasibility study on DRAM products with 66nm and 54nm design rules. The tool has shown high sensitivity to variations across an FEM wafer in both exposure and focus axes. In this article we show how PVM can help detection of Field to Field variations on DRAM wafers with 44nm design rule during normal production run. The complex die layout and the shrink in cell dimensions require high sensitivity to local variations within Dies or Fields. During normal scan of production wafers local Process variations are translated into GL (Grey Level) values, that later are grouped together to generate Process Variation Map and Field stack throughout the entire wafer.

Paper Details

Date Published: 1 April 2010
PDF: 11 pages
Proc. SPIE 7638, Metrology, Inspection, and Process Control for Microlithography XXIV, 76380B (1 April 2010); doi: 10.1117/12.848699
Show Author Affiliations
Dae Jong Kim, Hynix Semiconductor Inc. (Korea, Republic of)
Hyung Won Yoo, Hynix Semiconductor Inc. (Korea, Republic of)
Chul Hong Kim, Hynix Semiconductor Inc. (Korea, Republic of)
Hak Kwon Lee, Hynix Semiconductor Inc. (Korea, Republic of)
Sung Su Kim, Hynix Semiconductor Inc. (Korea, Republic of)
Koon Ho Bae, Hynix Semiconductor Inc. (Korea, Republic of)
Hedvi Spielberg, Applied Materials (Israel)
Yun Ho Lee, Applied Materials (Korea, Republic of)
Shimon Levi, Applied Materials (Israel)
Yariv Bustan, Applied Materials (Israel)
Moshe Rozentsvige, Applied Materials (Israel)


Published in SPIE Proceedings Vol. 7638:
Metrology, Inspection, and Process Control for Microlithography XXIV
Christopher J. Raymond, Editor(s)

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