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Proceedings Paper

Virtual fab flow for wafer topography aware OPC
Author(s): Hans-Jürgen Stock; Lars Bomholt; Dietmar Krüger; James Shiely; Hua Song; Nikolay Voznesenskiy
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Paper Abstract

Small feature sizes down to the current 45 nm node and precision requirements of patterning in 193 nm lithography as well as layers where the wafer stack does not allow any BARC require - not only correction of optical proximity (OPC) effects originating from mask topography and imaging system, but also correction of wafer topography proximity (WTPC) effects as well. In spite of wafer planarization process steps, wafer topography (proximity) effects induced by different optical properties of the patterned materials start playing a significant role, and correction techniques need to be applied in order to minimize the impact. In this paper, we study a methodology to create fast models intended for effective use in OPC and WTPC procedures. In order to be short we use the terms "OPCWTPC modeling" and "OPCWTPC models" through the paper although it would be more correctly to take the terms "mask synthesis modeling" and "mask synthesis models". A comprehensive data set is required to build a reliable OPC model. We present a "virtual fab" concept using extensive test pattern sets with both 1D and 2D structures to capture optical proximity effects as well as wafer topography effects. A rigorous lithography simulator taking into account exposure tool source maps, topographic mask effects as well as wafer topography is used to generate virtual measurement data, which are used for model calibration as well as for model validation. For model building, we use a two step approach: in a first step, an OPC model is built using test patterns on a planar, homogenous substrate; in a second step a WTPC model is calibrated, using results from simulated test patterns on shallow trench isolation (STI) layer. This approach allows building models from experimental data, including hybrid approaches where only experimental data from planar substrates is available and a corresponding OPC model for the planar case can be retrofitted with capabilities for correcting wafer topography effects. We analyze the relevant effects and requirements for model building and validation as well as the performance of fast WTPC models.

Paper Details

Date Published: 10 March 2010
PDF: 12 pages
Proc. SPIE 7640, Optical Microlithography XXIII, 76401U (10 March 2010); doi: 10.1117/12.848440
Show Author Affiliations
Hans-Jürgen Stock, Synopsys GmbH (Germany)
Lars Bomholt, Synopsys Switzerland LLC (Switzerland)
Dietmar Krüger, Synopsys GmbH (Germany)
James Shiely, Synopsys Inc. (United States)
Hua Song, Synopsys Inc. (United States)
Nikolay Voznesenskiy, Riia (Estonia)


Published in SPIE Proceedings Vol. 7640:
Optical Microlithography XXIII
Mircea V. Dusa; Will Conley, Editor(s)

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