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Proceedings Paper

Exploring complex 2D layouts for 22nm node using double patterning/double etch approach for trench levels
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Paper Abstract

With the delay of a next-node lithography solution, lithographers are required to evaluate double patterning techniques such as double pattern/double etch (DP/DE) to meet scaling targets for the 22nm logic node. The tightest design rule level to pattern has traditionally been the first metal level. For this node, target minimum pitches are below 32 nm half pitch in order to meet cell area requirements. In this paper, we explore implications of the DP/DE approach when applied to complex 2D metal patterns. In addition to evaluating stitching rules for line ends, we move into complicated patterning structures such as landing pads neighboring metal runners and arrays of dense landing pads. These feature types are critical for area scaling; however, when these structures are patterned in a DP/DE scheme, the minimum area of the features needed for each pattern layer can be quite small. In this work, we explore minimum area rules for stitching together patterns as function of overlap with first pattern, minimum area and proximity to unrelated trench features on the same pattern. These results are shown thru simulation and on the wafer scale using a DP/DE approach which uses current 28 nm node imaging techniques.

Paper Details

Date Published: 2 April 2010
PDF: 12 pages
Proc. SPIE 7641, Design for Manufacturability through Design-Process Integration IV, 76410A (2 April 2010); doi: 10.1117/12.848350
Show Author Affiliations
Scott W. Jessen, Texas Instruments Inc. (United States)
Steven L. Prins, Texas Instruments Inc. (United States)
James W. Blatchford, Texas Instruments Inc. (United States)
Brian W. Dillon, Photronics, Inc. (United States)
Christopher J. Progler, Photronics, Inc. (United States)

Published in SPIE Proceedings Vol. 7641:
Design for Manufacturability through Design-Process Integration IV
Michael L. Rieger; Joerg Thiele, Editor(s)

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