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Proceedings Paper

Implementing and validating double patterning in 22-nm to 16-nm product design and patterning flows
Author(s): Myung-Soo Noh; Beom-Seok Seo; Suk-Joo Lee; Alex Miloslavsky; Christopher Cork; Levi Barnes; Kevin Lucas
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Paper Abstract

In double-patterning technology (DPT), we study the complex interactions of layout creation, physical design and design rule checking flows for the 22nm and 16nm device nodes. Decomposition includes the cutting (splitting) of original design-intent features into new overlapping polygons where required; and the coloring of all the resulting polygons into two mask layouts. We discuss the advantages of geometric distribution for polygon operations with the limited range of influence. Further, we find that even the naturally global coloring step can be handled in a geometrically local manner. We analyze and compare the latest methods for designing, processing and verifying DPT methods including the 22nm and 16nm nodes.

Paper Details

Date Published: 3 March 2010
PDF: 11 pages
Proc. SPIE 7640, Optical Microlithography XXIII, 76400S (3 March 2010); doi: 10.1117/12.848194
Show Author Affiliations
Myung-Soo Noh, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Beom-Seok Seo, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Suk-Joo Lee, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Alex Miloslavsky, Synopsys (United States)
Christopher Cork, Synopsys SARL (France)
Levi Barnes, Synopsys Technology Park (United States)
Kevin Lucas, Synopsys Inc. (United States)

Published in SPIE Proceedings Vol. 7640:
Optical Microlithography XXIII
Mircea V. Dusa; Will Conley, Editor(s)

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