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Proceedings Paper

Systematic failure debug and defective pattern extraction for FPGA product yield improvement
Author(s): Cinti Chen; Joe W. Zhao; Ping Zhang; Raymond Y. Xu
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Paper Abstract

In this paper, we have presented an effective yield improvement methodology that can help both manufacturing foundries, fabless and fab-lite companies to identify systematic failures. It uses the physical addresses of failing bits from wafer sort results to overlay to inline wafer defect inspection locations. The inline defect patterns or the design patterns where overlay results showed matches were extracted and grouped by feature similarity or cell names. The potentially problematic design patterns can be obtained and used for design debug and process improvement.

Paper Details

Date Published: 3 April 2010
PDF: 9 pages
Proc. SPIE 7641, Design for Manufacturability through Design-Process Integration IV, 76410C (3 April 2010); doi: 10.1117/12.848185
Show Author Affiliations
Cinti Chen, Xilinx, Inc. (United States)
Joe W. Zhao, Xilinx, Inc. (United States)
Ping Zhang, Anchor Semiconductor, Inc. (United States)
Raymond Y. Xu, Anchor Semiconductor, Inc. (United States)


Published in SPIE Proceedings Vol. 7641:
Design for Manufacturability through Design-Process Integration IV
Michael L. Rieger; Joerg Thiele, Editor(s)

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