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Proceedings Paper

Mask enhancer technology for sub-100nm pitch random logic layout contact hole fabrication
Author(s): Takashi Yuito; Hiroshi Sakaue; Takashi Matsuda; Tadami Shimizu; Shigeo Irie; Fumio Iwamoto; Akio Misaka; Taichi Koizumi; Masaru Sasago
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Paper Abstract

We have proposed a new resolution enhancement technology using attenuated mask with phase shifting aperture, named "Mask Enhancer", for random-logic contact hole pattern printing. In this study, we apply Mask Enhancer on sub-100nm pitch contact hole printing with 1.35NA ArF immersion lithography tool, and ensure that Mask Enhancer can improve MEEF at resolution limit and DOF at semi-dense and isolated pitch region. We demonstrate printing a fine 100nm pitch line of contacts and isolated simultaneously with MEEF of less than 4 by using Mask Enhancer and prove that Mask Enhancer is one of the most effective solutions for random logic layout contact hole fabrication for 28nm node and below.

Paper Details

Date Published: 13 March 2010
PDF: 13 pages
Proc. SPIE 7640, Optical Microlithography XXIII, 76401B (13 March 2010); doi: 10.1117/12.848025
Show Author Affiliations
Takashi Yuito, Semiconductor Co., Panasonic Corp. (Japan)
Hiroshi Sakaue, Semiconductor Co., Panasonic Corp. (Japan)
Takashi Matsuda, Semiconductor Co., Panasonic Corp. (Japan)
Tadami Shimizu, Semiconductor Co., Panasonic Corp. (Japan)
Shigeo Irie, Semiconductor Co., Panasonic Corp. (Japan)
Fumio Iwamoto, Semiconductor Co., Panasonic Corp. (Japan)
Akio Misaka, Semiconductor Co., Panasonic Corp. (Japan)
Taichi Koizumi, Semiconductor Co., Panasonic Corp. (Japan)
Masaru Sasago, Semiconductor Co., Panasonic Corp. (Japan)


Published in SPIE Proceedings Vol. 7640:
Optical Microlithography XXIII
Mircea V. Dusa; Will Conley, Editor(s)

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