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Proceedings Paper

Realizing a 45-nm system on chip in the age of variability
Author(s): Laurent Le Cam; Andy Appleby; Philippe Hurat; Benoit Carpentier; Kuang-Han Chen; Nishath Verghese
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Paper Abstract

In this paper, we present the challenges of the realization of a large 45nm modern Media Processing SoC with multiple design teams distributed across many countries and time zones. We also describe the complex design methodology deployed to ensure the design is "closable" in the timing and manufacturability domain. Silicon variability impacts both the physical integrity and the parametric performance of the design. Lithography and CMP can cause enough context-dependent systematic variations, requiring exhaustive lithography and CMP physical verification and optimization of the layout. We present the physical and electrical DFM methodology at NXP. We will show how NXP has developed a manufacturing-aware design flow based on early prevention, detection and fixing using a hierarchical approach for model-based lithography checks and model-based CMP checks, from IP level to full-chip. We also present results of variability-aware timing sign-off.

Paper Details

Date Published: 10 March 2010
PDF: 10 pages
Proc. SPIE 7641, Design for Manufacturability through Design-Process Integration IV, 764106 (10 March 2010); doi: 10.1117/12.848023
Show Author Affiliations
Laurent Le Cam, NXP Semiconductors (Netherlands)
Andy Appleby, NXP Semiconductors (United Kingdom)
Philippe Hurat, Cadence Design Systems, Inc. (United States)
Benoit Carpentier, Cadence Design Systems (France)
Kuang-Han Chen, Cadence Design Systems, Inc. (United States)
Nishath Verghese, Cadence Design Systems, Inc. (United States)


Published in SPIE Proceedings Vol. 7641:
Design for Manufacturability through Design-Process Integration IV
Michael L. Rieger; Joerg Thiele, Editor(s)

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