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Proceedings Paper

Foundry verification of IP and incoming designs for manufacturing variability
Author(s): Li-Fu Chang; Julia Fu; Josh Yang; Elain Zou; Philippe Hurat; Nishath Verghese; Hua Ding
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Paper Abstract

With process technologies advancing to 65nm, 45nm, and below, device timing uncertainty due to lithography and other process variations has easily exceeded 50% and is still growing. In this paper, we present the development of a variability methodology, its correlation with silicon and application to cell and full-chip design verification and optimization. We describe both a methodology for variability analysis of standard cells and a full-chip screening methodology to identify potential chip variability excursions. This methodology relies on model-based analysis and integrates with our existing design-to-manufacturing flow. Based on silicon measurement data of one of our 65nm cell libraries, this methodology has achieved significant improvement in accuracy of estimating timing variations compared to a traditional rule-based method.

Paper Details

Date Published: 3 April 2010
PDF: 8 pages
Proc. SPIE 7641, Design for Manufacturability through Design-Process Integration IV, 76410F (3 April 2010); doi: 10.1117/12.848018
Show Author Affiliations
Li-Fu Chang, Semiconductor Manufacturing International Corp. (China)
Julia Fu, Semiconductor Manufacturing International Corp. (China)
Josh Yang, Semiconductor Manufacturing International Corp. (China)
Elain Zou, Semiconductor Manufacturing International Corp. (China)
Philippe Hurat, Cadence Design Systems, Inc. (United States)
Nishath Verghese, Cadence Design Systems, Inc. (United States)
Hua Ding, Cadence Design Systems, Inc. (China)


Published in SPIE Proceedings Vol. 7641:
Design for Manufacturability through Design-Process Integration IV
Michael L. Rieger; Joerg Thiele, Editor(s)

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