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Proceedings Paper

Reliability considerations in switchable PLL frequency synthesizers for wireless sensor networks
Author(s): Y. Liu; A. Srivastava
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Paper Abstract

In this work, reliability of communications systems in wireless sensor networks is addressed through the switchable phase-locked loops. The switchable phased-locked loop frequency synthesizer can work experimentally in a wide frequency range from 250 MHz to 700 MHz and is designed in 0.5μm n-well CMOS process. CMOS is the commonly used technology for communication systems wherein hot carrier injection and negative bias temperature instability are prime contributors to reliability. It is shown that both the hot carrier injection and negative bias temperature instability affect the performance of the phased-locked loop. The RMS jitter of the PLL increases by 40 ps and 23 ps for 4 hours of hot carrier injection and negative bias temperature instability stress, respectively. The experimental results show that the RMS jitter of the phase-locked loop varies from 30 ps to 123 ps as output frequency changes. The phase noise of phaselocked loop is -61 dBc/Hz at 10 kHz offset frequency and -104 dBc/Hz at 1 MHz offset frequency under 700 MHz phaselocked loop carrier frequency.

Paper Details

Date Published: 31 March 2010
PDF: 12 pages
Proc. SPIE 7646, Nanosensors, Biosensors, and Info-Tech Sensors and Systems 2010, 76460V (31 March 2010); doi: 10.1117/12.847664
Show Author Affiliations
Y. Liu, Louisiana State Univ. (United States)
A. Srivastava, Louisiana State Univ. (United States)


Published in SPIE Proceedings Vol. 7646:
Nanosensors, Biosensors, and Info-Tech Sensors and Systems 2010
Vijay K. Varadan, Editor(s)

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