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Proceedings Paper

45nm-generation parameter-specific ring oscillator monitors
Author(s): Lynn T.-N. Wang; Nuo Xu; Tsu-Jae King Liu; Andrew R. Neureuther
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Paper Abstract

Experimental results are reported for ring oscillators (ROs) fabricated using 45nm generation CMOS technology and inverter layouts that are designed to identify and quantify sources of circuit performance variation due to gate etch/lithography, gate-to-active misalignment, and CESL-induced stress. The measured RO frequency data show that within-chip variation is negligible in comparison with chip-to-chip variation. Standard-deviation over mean (σ/μ) values among 36 RO instances show a slight channel area dependence of 0.2% versus sqrt(area)-1. For a typical wafer, 3% RO frequency change due to gate etch/focus variations, 2-3nm overlay error, and a 5% increase by doubling the length of diffusion (LOD) can be measured.

Paper Details

Date Published: 3 April 2010
PDF: 9 pages
Proc. SPIE 7641, Design for Manufacturability through Design-Process Integration IV, 76410N (3 April 2010); doi: 10.1117/12.846719
Show Author Affiliations
Lynn T.-N. Wang, Univ. of California, Berkeley (United States)
Nuo Xu, Univ. of California, Berkeley (United States)
Tsu-Jae King Liu, Univ. of California, Berkeley (United States)
Andrew R. Neureuther, Univ. of California, Berkeley (United States)


Published in SPIE Proceedings Vol. 7641:
Design for Manufacturability through Design-Process Integration IV
Michael L. Rieger; Joerg Thiele, Editor(s)

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