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Proceedings Paper

45nm transistor variability study for memory characterization
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Paper Abstract

We have previously analyzed spatial process variation using 45nm ring oscillator arrays. Our hierarchical variability model had proven to be very useful in revealing interesting systematic patterns, and in separating them from native random variability. To further understand the underlying mechanism of the process variation, we continue to work on the analysis and modeling of spatial variation of transistors made on the same 45nm technology test chips. A novel statistical compact device modeling procedure is used to extract the systematic and random variation of device parameters across wafer and within die. Statistical SPICE simulation is then performed based on the extracted variation model of device parameters. The results compare well with actual ring oscillator and SRAM measurements, in that the characteristic systematic, spatial and random patterns have been captured for circuit-level simulation.

Paper Details

Date Published: 3 April 2010
PDF: 12 pages
Proc. SPIE 7641, Design for Manufacturability through Design-Process Integration IV, 76410G (3 April 2010); doi: 10.1117/12.846704
Show Author Affiliations
Kun Qian, Univ. of California, Berkeley (United States)
Costas J. Spanos, Univ. of California, Berkeley (United States)


Published in SPIE Proceedings Vol. 7641:
Design for Manufacturability through Design-Process Integration IV
Michael L. Rieger; Joerg Thiele, Editor(s)

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